1. Field of the Invention
The present invention relates generally to a low reflection driver for a high speed simultaneous bi-directional transmission line/data bus which is designed such that units at both ends of the transmission line/data bus can transmit data at any time without waiting for the bus to become available so that the baud rate of the bus is increased. The present invention also relates generally a PCB (printed circuit board) having thereon at least the low reflection driver for the high speed simultaneous bi-directional transmission line/data bus and a method of transmitting high speed simultaneous bi-directional data over a transmission line/data bus.
A push-pull current source driver for the bi-directional simultaneous data bus provides greater flexibility for an output voltage swing, a matching impedance and bandwidth compensation. The push-pull current source driver minimizes external components such as an analog delay line and provides an easy PCB (printed circuit board) design.
2. Discussion of the Prior Art
FIG. 1 illustrates a conventional simultaneous bi-directional data bus structure and system consisting of identical units, Unit A and Unit B, at opposite ends of a data bus/transmission line TL having a characteristic impedance Z0. Each unit has a driver and a receiver.
The driver is similar to an inverter with two resistors wherein Rpa=Rna=Rpb=Rnb=Z0, the characteristic impedance of the transmission line TL. Pa, Pb are pfets, and Na and Nb are nfets.
Table 1 (second and third lines) shows the voltages at CA and CB when Va and Vb are at different logic states.
TABLE 1VaVbPaNaPbNbCACBLogic 0Logic 0ONOFFONOFFVccVccState 0(0 V)(0 V)Logic 0Logic 1ONOFFOFFONVcc/2Vcc/2State 1(0 V)(Vcc)Logic 1Logic 0OFFONONOFFVcc/2Vcc/2State 2(Vcc)(0 V)Logic 1Logic 1OFFONOFFON00State 3(Vcc)(Vcc)
In operation, unit A can detect the logic signal Vb sent from the unit B based on the voltage on CA and the logic state at Va, e.g. if Va=0 and CA is Vcc, Vb is determined as logic 0 (State 0), and if Va=1 and CA is 0, Vb is determined as logic 1 (State 3).
The problems with the prior art driver structure are:
1. Impedance Mismatch: When the data rate is high, the impedance match of the transmission line TL and the termination is very important. If the impedances are mismatched, reflection occurs, which seriously increases jitter and error bits. When Va or Vb are at Vcc or 0V, the transmission line TL has a good impedance match because Rpa=Rna=Rpb=Rnb=Z0, the nfet is turned on completely, presenting a very low impedance, the pfet is cut off, presenting a very high impedance, or the nfet is cut off, presenting a very high impedance, and the pfet is turned on completely, presenting a very low impedance. But when the voltage on Va or Vb sweeps across Vcc/2, both the nfet and the pfet are in a saturation mode, presenting a high impedance, and the termination impedance at that moment is much higher than Z0 the characteristic impedance of TL. If at that moment, a transition arrives at CA or CB, the impedance mismatch results in a large reflection. A problem with impedance matching in the simultaneous bi-directional data bus occurs when an input signal edge arrives at the same time the driver is switching states, which results in the output impedance mismatching the transmission line characteristic impedance, resulting in a serious signal reflection.
2. Parasitic Capacitance: Parasitic capacitance on CA or CB increases the coming signal rise time and fall time, resulting in increased jitter.